1. Field of the Invention
The present invention relates to a local charge storing memory device. More particularly, the present invention relates to a memory device with multiple memory layers of local charge storage.
2. The Background Art
There are a variety of non-volatile memory devices known to those of ordinary skill in the art. These include antifuses, floating gate transistors, and floating trap transistors. An antifuse is a programmable device that includes a first and second electrode having a dielectric disposed between the first and second electrodes. It is an open state until programmed. It is programmed by placing a voltage across the first and second electrodes sufficient to cause current to flow between the electrodes to form a conductive link between the electrodes. Once programmed, the antifuse provides a conductive path between conductive lines coupled to the first and second electrodes of the antifuse.
A floating gate transistor is an MOS based device having an unconnected or floating polysilicon layer disposed in a dielectric between the semiconductor surface and the gate of the MOS transistor. There are a variety of known floating gate transistor technologies. These differences in the art are due at least in some instances to the specific geometry of the floating gate, the distance from the semiconductor surface of the floating gate in the dielectric, the inclusion of additional gates in the MOS transistor of the floating gate memory cell, the manner in which electrons are placed on and removed from the floating gate, and the diverse arrangements of the floating gate transistors into memory cell arrays. These various technologies, well known to those of ordinary skill in the art, include electrically programmable read only memory (EPROM), electrically erasable and programmable read only memory (EEPROM), flash EEPROM, NOR flash and NAND flash.
To program the floating gate transistor, electrons are placed on the floating polysilicon layer, and to erase the floating gate memory cell, electrons are removed from the floating polysilicon layer. According to the particular floating gate transistor technology involved, electrons are (a) placed onto the floating gate; and (b) removed from the floating gate by a combination of (a) channel hot electron injection or Fowler-Nordheim tunneling; and (b) UV light, hot hole injection or Fowler-Nordheim tunneling, respectively. Each of these methods for placing and removing electrons on the floating gate requires the gate, source, drain and substrate of the floating gate transistor to either be biased to voltages relative to one another or to float for a time sufficient to either program or erase the floating gate transistor.
A floating gate memory cell is programmed when sufficient electrons are placed on the floating polysilicon layer to prevent the MOS transistor of the floating gate memory cell from being turned on. The charged floating polysilicon layer opposes a voltage which, when applied to the gate of the floating gate memory cell would typically turn-on the MOS transistor of the floating gate memory cell. When these electrons are removed, a normal operating voltage applied to the gate of floating gate transistor will result in current flowing through the MOS transistor of the floating gate memory cell. This current may then be sensed to determine whether a particular floating gate memory cell has been programmed.
Conventional floating gate memory cells have some performance characteristics such as long programming and erase times, high programming voltages, insufficient data retention times, limited number of programming cycles, and large integrated circuit area requirements which have led to the investigation and development of local charge storage MOS transistors such as floating trap MOS transistors and floating gate silicon nanocrystal MOS transistors.
In FIG. 1, an n-channel floating trap MOS transistor 10 according to the prior art is illustrated schematically in cross section. In n-channel floating trap MOS transistor 10, a p-type region 12 formed by a p-type semiconductor substrate or p-type well formed in a semiconductor substrate has a first n-type source/drain (S/D) region 14 and a second n-channel source/drain region 16. A lower silicon dioxide layer 18 of about 20 to about 60 angstroms in thickness is disposed above the p-type region 12 and a portion of the source and drain regions 14 and 16, respectively. A silicon nitride layer 20 of about 60 to about 80 angstroms in thickness is disposed above the silicon dioxide layer 18. The silicon nitride layer 20 forms a floating trap layer that traps electrons as they are injected across the oxide layer 18 and into the nitride layer 20. An upper layer of silicon dioxide 22 of about 60 angstroms is formed over the nitride layer 20. A polysilicon or metal conductive control gate 24 is disposed above the upper oxide layer 22. The upper oxide layer 22 functions to electrically isolate the conductive gate 24 from floating trap 20.
Two well known, and similar floating trap transistor technologies include silicon-oxide-nitride-oxide-silicon (SONOS) and metal-oxide-nitride-oxide-silicon (MONOS). In each of these devices, the dielectric separating the gate of the MOS transistor from the semiconductor substrate is an oxide-nitride-oxide (ONO) layer. In a recent advance in the floating trap transistor technology of MONOS/SONOS devices, a thicker bottom oxide layer in the ONO dielectric has been employed to improve charge retention and to reduce read disturb.
In a floating trap MOS transistor, charge is stored (trapped) in or removed from after being trapped in, a dielectric separating the gate of the MOS transistor from the semiconductor substrate. Unlike a floating gate transistor, where charge stored on the polysilicon conductor may flow freely within the polysilicon conductor, charge stored in a floating trap MOS transistor is localized to the region of the floating trap material above the source or drain where it was originally placed during programming. Accordingly, a bit of information may be stored above each of the junctions of a floating trap MOS transistor for a total of two bits. To program a floating trap MOS transistor device both channel hot electron injection and Fowler-Nordheim tunneling have been employed. To erase a floating trap MOS transistor device both Fowler-Nordheim tunneling and tunneling enhanced hot hole injection have been employed.
In FIG. 2A, a table indicates the voltages applied to the floating trap MOS transistor 10 depicted in FIG. 1 for programming by channel hot electron injection in either a Substrate Ground Mode or a Substrate Enhanced Mode. As set forth therein, in the Substrate Ground Mode wherein the substrate 12 is at about 0 volts, the gate 24 is held at about 9 volts to about 12 volts, and the first source/drain 14 of n-channel floating trap MOS transistor above whose junction the electrons are to be trapped is held at about 0 volts, while the second source/drain 16 of the n-channel floating trap MOS transistor is held at about 4 volts to about 5 volts. In the Substrate Enhanced Mode wherein the substrate 12 is at about −2 volts to about −3 volts, the gate 24 is held at about 6 volts to about 8 volts, and the first source/drain 14 of n-channel floating trap MOS transistor above whose junction the electrons are to be trapped is held at about 0 volts, while the second source/drain 16 of the n-channel floating trap MOS transistor is held at about 3 volts to about 4 volts. The programming time for channel hot electron injection is about 1 ms to about 5 ms.
In FIG. 2B, a table indicates the voltages applied to the floating trap MOS transistor 10 depicted in FIG. 1 for programming by Fowler-Nordheim tunneling in either a Substrate Ground Mode or a Substrate Enhanced Mode. With Fowler-Nordheim tunneling, both of the areas above the junctions of the first and second source/drain regions 14 and 16, respectively, are programmed at the same time. As set forth therein, in the Substrate Ground Mode wherein the substrate 12 is at about 0 volts, the gate 24 is held at about 12 volts to about 15 volts, and the first source/drain 14 of n-channel floating trap MOS transistor is held at about 0 volts or allowed to float, while the second source/drain 16 of the n-channel floating trap MOS transistor is held at about 0 volts or allowed to float. In the Substrate Enhanced Mode wherein the substrate 12 is at about −6 volts to about −8 volts, the gate 24 is held at about 6 volts to about 8 volts, and the first source/drain 14 and the second source/drain 16 of n-channel floating trap MOS transistor are held at about −6V to −8 volts or allowed to float. The programming time for Fowler-Nordheim tunneling is about 2 ms to 20 ms.
In FIG. 2C, a table indicates the voltages applied to the floating trap MOS transistor 10 depicted in FIG. 1 for erasing either one or both areas above the source/drain junctions of source/drain regions 14 and 16, respectively, by hot hole injection in either a Substrate Ground Mode or a Substrate Enhanced Mode. As set forth therein, in the one-sided Substrate Ground Mode wherein the substrate 12 is at about 0 volts, the gate 24 is held at about −10 volts to about −12 volts, and the first source/drain 14 of n-channel floating trap MOS transistor above whose junction the electrons are to be erased is held at about 5 volts to about 6 volts, while the second source/drain 16 of the n-channel floating trap MOS transistor is allowed to float. In the one-sided Substrate Enhanced Mode wherein the substrate 12 is at about −2 volts to about −3 volts, the gate 24 is held at about −6 volts to about −8 volts, and the first source/drain 14 of n-channel floating trap MOS transistor above whose junction the electrons are to be erased is held at about 3 volts to about 4 volts, while the second source/drain 16 of the n-channel floating trap MOS transistor is allowed to float. In the two-sided Substrate Ground Mode wherein the substrate 12 is at about 0 volts, the gate 24 is held at about −10 volts to about −12 volts, and the first and second source/drain regions 14 and 16, respectively, of n-channel floating trap MOS transistor above whose junction the electrons are to be erased are held at about 5 volts to about 6 volts. In the two-sided Substrate Enhanced Mode wherein the substrate 12 is at about −2 volts to about −3 volts, the gate 24 is held at about −6 volts to about −8 volts, and the first and second source/drain regions 14 and 16, respectively, of n-channel floating trap MOS transistor above whose junction the electrons are to be erased are held at about 5 volts to about 6 volts. The erase time for hot hole injection is about 1 ms to 5 ms.
In FIG. 2D, a table indicates the voltages applied to the floating trap MOS transistor 10 depicted in FIG. 1 for erasure by Fowler-Nordheim tunneling in either a Substrate Ground Mode or a Substrate Enhanced Mode. With Fowler-Nordheim tunneling, both of the areas above the junctions of the first and second source/drain regions 14 and 16, respectively, are erased at the same time. As set forth therein, in the Substrate Ground Mode wherein the substrate 12 is at about 0 volts, the gate 24 is held at about −12 volts to about −15 volts, and the first source/drain 14 of n-channel floating trap MOS transistor is held at about 0 volts or allowed to float, while the second source/drain 16 of the n-channel floating trap MOS transistor is held at about 0 volts or allowed to float. In the Substrate Enhanced Mode wherein the substrate 12 is at about 6 volts, the gate 24 is held at about −6 volts to about −8 volts, and the first source/drain 14 of n-channel floating trap MOS transistor is held at about 0 volts or allowed to float, while the second source/drain 16 of the n-channel floating trap MOS transistor is held at about 0 volts or allowed to float. The erasure time for Fowler-Nordheim tunneling is about 2 ms to 20 ms.
In FIG. 2E, a table indicates the voltages applied to the floating trap MOS transistor depicted in FIG. 1 for reading the floating trap MOS transistor in a Substrate Ground Mode. As set forth therein, in a n-channel floating trap MOS transistor with the p-type substrate 12 at about 0 volts, to read the charge trapped above a first junction associated with a first source/drain region 14 of the n-channel floating trap MOS transistor 10, the gate 24 of the n-channel floating trap MOS transistor 10 is held at about 3 volts to about 4 volts, and the first source/drain 14 of n-channel floating trap MOS transistor above whose junction the electrons are to be read is held at about 1 volt to about 2 volts, while the second source/drain 16 of the n-channel floating trap MOS transistor is held at about 0 volts. During the read, a sense of the current through the n-channel floating trap MOS transistor is performed to determine the programmed state of the floating trap device. In U.S. Pat. No. 5,768,192, a charge trapping device is described that is programmed using channel hot electron injection, and erased with tunneling enhanced hot hole injection. As described therein, a reverse read scheme is employed to enhance charge read sensitivity, wherein a read of the charge trapped above a first junction associated with a first source/drain region of an n-channel floating trap MOS transistor is performed by applying about 0 volts to a p-type substrate while applying about 3 volts to about 4 volts to the gate of the n-channel floating trap MOS transistor, 0 volts to the first source/drain region of the n-channel floating trap MOS transistor above whose junction the electrons are to be read, and about 1 volt to about 2 volts to a second source/drain 16 of the n-channel floating trap MOS transistor.
In FIG. 3, an n-channel floating gate silicon nanocrystal MOS transistor 30 according to the prior art is illustrated schematically in cross section. In n-channel floating gate silicon nanocrystal MOS transistor 30, a p-type region 32 formed by a p-type semiconductor substrate or p-type well formed in a semiconductor substrate has a first n-type source/drain (S/D) region 34 and a second n-channel source/drain region 36. A lower silicon dioxide layer 38 of about 20 to about 60 angstroms in thickness is disposed above the p-type region 32 and a portion of the source and drain regions 34 and 36, respectively. A layer of silicon nanocrystals 40 typically having diameters of about 40 angstroms to about 100 angstroms and spaced apart by about 40 angstroms to about 60 angstroms is disposed above the silicon dioxide layer 38. The silicon nanocrystal layer 40 forms a floating gate that traps charge as it is injected across the oxide layer 38 and into the silicon nanocrsytal layer 40. An upper layer of silicon dioxide 42 of about 60 angstroms is formed over the silicon nanocrystal layer 40. A polysilicon or metal conductive control gate 44 is disposed above the upper oxide layer 42. The upper oxide layer 42 functions to electrically isolate the conductive gate 44 from floating gate 40.
In a floating gate silicon nanocrystal MOS transistor, charge is stored (trapped) in or removed from after being trapped in the silicon nanocrystals. Unlike a conventional floating gate transistor, where charge stored on the polysilicon conductor may flow freely in the polysilicon conductor, charge stored in a floating gate silicon nanocrystal MOS transistor is localized to the region of the floating nanocrystal material above the source or drain where it was originally placed during programming. Accordingly, a bit of information may be stored above each of the junctions of a nanocrystal based MOS transistor for a total of two bits. This two-bit charge storage is analogous to the two-bit charge storage provided by a floating trap MOS transistor such as SONOS or MONOS. To program a floating gate silicon nanocrystal MOS transistor device both channel hot electron injection and Fowler-Nordheim tunneling have been employed. To erase a floating trap MOS transistor device both Fowler-Nordheim tunneling and tunneling enhanced hot hole injection have been employed
In FIG. 4A, a table indicates the voltages applied to the floating gate silicon nanocrystal MOS transistor 30 depicted in FIG. 3 for programming by channel hot electron injection in either a Substrate Ground Mode or a Substrate Enhanced Mode. As set forth therein, in the Substrate Ground Mode wherein the substrate 32 is at about 0 volts, the gate 44 is held at about 8 volts to about 9 volts, and the first source/drain 34 of n-channel floating gate silicon nanocrystal MOS transistor 30 above whose junction the electrons are to be trapped is held at about 0× volts, while the second source/drain 36 of the n-channel floating gate silicon nanocrystal MOS transistor is held at about 4 volts to about 5 volts. In the Substrate Enhanced Mode wherein the substrate 32 is at about −2 volts to about −3 volts, the gate 44 is held at about 6 volts to about 8 volts, and the first source/drain 34 of n-channel floating gate silicon nanocrystal MOS transistor above whose junction the electrons are to be trapped is held at about 0 volts, while the second source/drain 36 of the n-channel floating gate silicon nanocrystal MOS transistor is held at about 3 volts to about 4 volts. The programming time for channel hot electron injection is about 1 ms to about 5 ms.
In FIG. 4B, a table indicates the voltages applied to the floating gate silicon nanocrystal MOS transistor 30 depicted in FIG. 3 for programming by Fowler-Nordheim tunneling in either a Substrate Ground Mode or a Substrate Enhanced Mode. With Fowler-Nordheim tunneling, both of the areas above the junctions of the first and second source/drain regions 34 and 36, respectively, are programmed at the same time. As set forth therein, in the Substrate Ground Mode wherein the substrate 32 is at about 0 volts, the gate 44 is held at about 12 volts to about 14 volts, and the first source/drain 34 of n-channel floating trap MOS transistor is held at about 6 volts to about 7 volts, while the second source/drain 36 of the n-channel nanocrystal MOS transistor is held at about 6 volts to about 7 volts or allowed to float. In the Substrate Enhanced Mode wherein the substrate 32 is at about −6 volts to about −8 volts, the gate 44 is held at about 6 volts to about 8 volts, and the first source/drain 34 of n-channel nanocrystal MOS transistor is held at about −6 volts to about −8 volts, while the second source/drain 36 of the n-channel floating gate silicon nanocrystal MOS transistor is held at about −6 volts to about −8 volts. The programming time for Fowler-Nordheim tunneling is about 2 ms to 20 ms.
In FIG. 4C, a table indicates the voltages applied to the floating gate silicon nanocrystal MOS transistor 30 depicted in FIG. 3 for erasing either one or both areas above the source/drain junctions of source/drain regions 34 and 36, respectively, by hot hole injection in either a Substrate Ground Mode or a Substrate Enhanced Mode. As set forth therein, in the one-sided Substrate Ground Mode wherein the substrate 32 is at about 0 volts, the gate 44 is held at about −10 volts to about −12 volts, and the first source/drain 34 of n-channel floating trap MOS transistor above whose junction the electrons are to be erased is held at about 5 volts to about 6 volts, while the second source/drain 36 of the n-channel floating trap MOS transistor is allowed to float. In the one-sided Substrate Enhanced Mode wherein the substrate 32 is at about −2 volts to about −3 volts, the gate 44 is held at about −6 volts to about −8 volts, and the first source/drain 44 of n-channel floating gate silicon nanocrystal MOS transistor above whose junction the electrons are to be erased is held at about 3 volts to about 4 volts, while the second source/drain 36 of the n-channel floating gate silicon nanocrystal MOS transistor is allowed to float. In the two-sided Substrate Ground Mode wherein the substrate 32 is at about 0 volts, the gate 44 is held at about −10 volts to about −12 volts, and the first and second source/drain regions 34 and 36, respectively, of n-channel floating gate silicon nanocrystal MOS transistor above whose junction the electrons are to be erased are held at about 5 volts to about 6 volts. In the two-sided Substrate Enhanced Mode wherein the substrate 32 is at about −2 volts to about −3 volts, the gate 44 is held at about −6 volts to about −8 volts, and the first and second source/drain regions 34 and 36 respectively, of n-channel floating gate silicon nanocrystal MOS transistor above whose junction the electrons are to be erased are held at about 5 volts to about 6 volts. The erase time for hot hole injection is about 1 ms to 5 ms.
In FIG. 4D, a table indicates the voltages applied to the floating gate silicon nanocrystal MOS transistor 30 depicted in FIG. 3 for erasure by Fowler-Nordheim tunneling in either a Substrate Ground Mode or a Substrate Enhanced Mode. With Fowler-Nordheim tunneling, both of the areas above the junctions of the first and second source/drain regions 34 and 36, respectively, are erased at the same time. As set forth therein, in the Substrate Ground Mode wherein the substrate 32 is at about 0 volts, the gate 44 is held at about −12 volts to about −15 volts, and the first source/drain 34 of n-channel floating gate silicon nanocrystal MOS transistor is held at about 0 volts or allowed to float, while the second source/drain 36 of the n-channel floating gate silicon nanocrystal MOS transistor is held at about 0 volts or allowed to float. The erasure time for Fowler-Nordheim tunneling is about 2 ms to 20 ms.
In FIG. 4E, a table indicates the voltages applied to the floating gate silicon nanocrystal MOS transistor 30 depicted in FIG. 3 for reading the floating gate silicon nanocrystal MOS transistor in a Substrate Ground Mode. As set forth therein, in a n-channel floating gate silicon nanocrystal MOS transistor with the p-type substrate 32 at about 0 volts, to read the charge trapped above a first junction associated with a first source/drain region 34 of the n-channel floating gate silicon nanocrystal MOS transistor 30, the gate 44 of the n-channel floating gate silicon nanocrystal MOS transistor 30 is held at about 3 volts to about 4 volts, and the first source/drain 34 of n-channel floating gate silicon nanocrystal MOS transistor above whose junction the electrons are to be read is held at about 1 volt to about 2 volts, while the second source/drain 36 of the n-channel floating gate silicon nanocrystal MOS transistor is held at about 0 volts. During the read, a sense of the current through the n-channel floating gate silicon nanocrystal MOS transistor is performed to determine the programmed state of the floating gate silicon nanocrystal device.